1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an MRAM (Magnetic Random Access Memory) using a TMR (Tunneling Magneto Resistive) element as a memory element.
2. Description of the Related Art
Recently, an MRAM (Magnetic Random Access Memory) cell using a magneto resistive element as a data memory element has been proposed. This MRAM is expected to advance to a nonvolatile, highly integrated, reliable, high-speed memory device.
As magneto resistive elements, principally a GMR (Giant Magneto Resistive) element and a TMR (Tunneling Magneto Resistive) element are known. A GMR element is composed of two ferromagnetic layers and a conductor sandwiched between these ferromagnetic layers. The effect of this GMR element is that the resistance of this conductor changes in accordance with spin directions in the upper and lower ferromagnetic layers. However, the MR (Magneto Resistive) ratio of the GMR element is as low as 10% or less, so a read margin is difficult to ensure. A TMR element is composed of two ferromagnetic layers and an insulator sandwiched between these ferromagnetic layers. The effect of this TMR element is that the tunnel resistance of this insulator changes in accordance with spin directions in the upper and lower ferromagnetic layers. Presently, the TMR element can assure an MR ratio of 50% or more.
FIGS. 24A to 26B illustrate representative semiconductor memories having TMR elements fabricated by prior art references. That is, FIGS. 24A to 26B depict the cell structures of memory cell portions of these semiconductor memories.
FIG. 24A is a plan view of a semiconductor memory device according to the first prior art. FIG. 24B is a sectional view of this semiconductor memory device taken along a line XXIVB—XXIVB in FIG. 24A. The semiconductor memory device according to this first prior art has a structure which uses a MOS transistor as a switching element connected to a TMR element.
As shown in FIGS. 24A and 24B, a plurality of bit lines 13 and a plurality of write word lines 14 run in a matrix manner so as to cross each other at right angles, and a TMR element 11 is formed at each cross point. This TMR element 11 is connected to the bit line 13 via an upper electrode (not shown), and to a MOS transistor 35 via a lower electrode 70 and a contact layer 38. A gate electrode 33 of this MOS transistor 35 is a read word line. The TMR element 11 is composed of a ferroelectric magnetization fixing layer 41 connected to the lower electrode 70, a ferroelectric magnetic recording layer 43 connected to the bit line 13 via the upper electrode, and a nonmagnetic tunnel junction layer 42 sandwiched between the magnetization fixing layer 41 and the magnetic recording layer 43.
In this semiconductor memory device, data is written and read out as follows.
The magnetization reversal threshold value of the magnetization fixing layer 41 is higher than that of the magnetic recording layer 43. In a normal write operation, therefore, the magnetization direction in the magnetization fixing layer 41 does not reverse, and only the magnetization direction in the magnetic recording layer 43 reverses. Accordingly, to write data into a given selected cell, the magnetization direction in the magnetic recording layer 43 is reversed to write data “1” or “0” into the selected cell. More specifically, to write data into a given selected cell, it is necessary to use at least two write lines (the bit line 13 and the write word line 14) and reverse the magnetization direction in the magnetic recording layer 43 only at the cross point of these two write lines.
The resistance of the tunnel junction layer 42 is lowest when the magnetization directions in the magnetic recording layer 43 and the magnetization fixing layer 41 are equal; the resistance of the tunnel junction layer 42 is highest when these two magnetization directions are anti-parallel. Hence, a change in the resistance of this tunnel junction layer 42 is detected by allowing an electric current to flow through the TMR element 11 from the two, upper and lower lines via the upper electrode and the lower electrode 70 sandwiching the TMR element 11 from the outside. Since this makes it possible to discriminate between the data “1” and “0” storage states, the data is read out.
FIG. 25A is a plan view of a semiconductor memory device according to the second prior art. FIG. 25B is a sectional view of this semiconductor memory device taken along a line XXVB—XXVB in FIG. 25A. The semiconductor memory device according to this second prior art has a structure using a rectifying element (e.g., a p-n junction diode) 12 as a switching element connected to a TMR element 11. This structure is a simple one capable of realizing a cross point cell. In this structure, a write line for writing data into a magnetic recording layer 43 and a read line for reading data from the magnetic recording layer 43 are common lines. Therefore, data write and read operations are performed only by two lines, a word line 14 and a bit line 13. To write or read data only in or from a selected cell by using the rectification properties of the diode 12, biases applied to the word line 14 and the bit line 13 must be separately controlled.
FIG. 26A is a plan view of a semiconductor memory device according to the third prior art. FIG. 26B is a sectional view of this semiconductor memory device taken along a line XXVIB—XXVIB in FIG. 26A. The semiconductor memory device according to this third prior art has the same cross point structure as the semiconductor memory device according to the second prior art, except that no rectifying element is used. Since no rectifying element is used, the process and structure are simple. However, a read operation requires some scheme because an electric current flows through cells other than a selected cell when data is read out. That is, data is written in a selected cell by using two lines, a read word line 14b and a write word line 14a, and data in a selected cell is read out by using two lines, a bit line 13 and the read word line 14b. In this manner, a cell is accessed using a total of three lines by using one of the read and write lines as a common line.
As shown in FIG. 27, the semiconductor memory device according to any of the above prior art references has a memory cell portion 10 and a peripheral circuit portion 20 for controlling this memory cell portion 10. Since circuits of this peripheral circuit portion 20 are formed outside the memory cell portion 10, only TMR elements 11 and switching elements are formed in the memory cell portion 10.
Accordingly, as shown in FIG. 24B, the semiconductor memory device according to the first prior art has an unused space 45 in the memory cell portion 10. Also, as shown in FIGS. 25B and 26B, each of the semiconductor memories according to the second and third prior art references has an unused space 45, because the entire surface of a semiconductor substrate 30 present below the memory cell portion 10 is merely an element isolation region 32. These spaces 45 are obstacles to further reduce the MRAM mounting chip area.